An on-chip self-repair calculation and fusing methodology

Laser fusing is a standard technique for improving yield with memory reconfiguration and repair, but implementing fusing in production can be challenging and costly. This article introduces an electrically programmable polysilicon fuse and shows how it can reduce fuse area and programming complexity.

[1]  Steven F. Oakland,et al.  On-chip repair and an ATE independent fusing methodology , 2002, Proceedings. International Test Conference.

[2]  Howard Leo Kalter,et al.  Processor-based built-in self-test for embedded DRAM , 1998, IEEE J. Solid State Circuits.

[3]  Michael R. Ouellette,et al.  Shared fuse macro for multiple embedded memory devices with redundancy , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[4]  N. Kushiyama,et al.  A 1.6 GB/s DRAM with flexible mapping redundancy technique and additional refresh scheme , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[5]  B.J. Park,et al.  A 0.13 /spl mu/m logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 /spl mu/m generation , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[6]  K. Dosaka,et al.  An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).