A 2GHz, 7W (max) 64b PowerTM Microprocessor Core
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Fang Liu | Shyam Sundar | Zhibin Huang | Eric Wu | Fabian Klass | Sribalan Santhanam | Brian Campbell | Hang Huang | James Burnette | Naveen Javarappa | Rajat Goel | Daniel Murray | Mark Chung | Bruce Fernandes | Subhendra Ghosh | Greg Hess | Pradeep Kanapathipillai | Anup Mehta | Yamini Modukuru | Nishant Nerurkar | Abhijit Radhakrishnan | Junji Sugisawa | Honkai John Tam | Ricky Wen | Jung-Cheng Yeh | John Yong | Sanjay Zambare
[1] Tse-Yu Yeh. Low-Power, High-Performance Architecture of the PWRficient Processor Family , 2006, IEEE Micro.
[2] Hao Chen,et al. A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[3] Brian Campbell,et al. Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[4] Kazuo Yano,et al. A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .
[5] F. Weber,et al. Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.