Simulation and Evaluation of a Network on Chip Architecture Using Ns-2

-A new chip design paradigm called Network on Chip (NOC) offers a promis architectural choice for future systems on chips. NOC architectures offer a packet swit communication among functional cores on the chip. NOC architectures also apply con from computer networks and organize on-chip communication among cores in layers si to OSI reference model. We constructed a protomodel using a public domain network sim ns-2 and evaluated design options for a specific NOC architecture which has a dimensional mesh of switches. In particular, we analysed the series of simulation results the relationship between buffer size in switch, communication load, packet delay and p drop probability. All the results are useful for design of an appropriate switch for the NO