Characterization and suppression of drain coupling in submicrometer EPROM cells

The EPROM transistor suffers from a capacitive-coupling-based short-channel effect called drain turn-on or Vdtothat limits the maximum drain voltage. Several measurement techniques are demonstrated to characterize the Vdtoeffect. An analytical model is applied to the problem to estimate the effects of process variations to suppress the phenomenon. The effect of Vdtoon scaling is discussed, and circuit and device design techiques to reduce or eliminate this problem are discussed.

[1]  P.K. Ko,et al.  An analytical model for intrinsic capacitances of short-channel MOSFETs , 1984, 1984 International Electron Devices Meeting.

[2]  Pallab K. Chatterjee,et al.  Modelling of small MOS devices and device limits , 1983 .

[3]  K. Makita,et al.  A new EPROM cell with a side-wall floating gate for high-density and high-performance device , 1985, 1985 International Electron Devices Meeting.

[4]  R. Shrivastava,et al.  A simple model for the overlap capacitance of a VLSI MOS device , 1982, IEEE Transactions on Electron Devices.

[5]  B. Eitan,et al.  Surface conduction in short-channel MOS devices as a limitation to VLSI scaling , 1982, IEEE Transactions on Electron Devices.