A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS

It has been well understood that the digital clock and data recovery (CDR) architecture has many system merits over the analog counterpart for multi-Gb/s transceivers [1]. However, the applications have been limited in systems where the clock is forwarded or has small frequency offset [2, 3], due to the finite frequency and jitter tracking capability of the digitally controlled phase rotation. Recently, tracking range up to ±7800ppm has been reported [4] to extend the applications to the SATA/SAS interfaces that require 5000ppm spread spectrum clocking (SSC) to suppress electromagnetic emissions. To enable broad acceptance in high-speed applications, the digital CDRs must have much wider tracking range.

[1]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

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[3]  Simone Erba,et al.  A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication , 2009, IEEE Journal of Solid-State Circuits.

[4]  John T. Stonick,et al.  A digital clock and data recovery architecture for multi-gigabit/s binary links , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[5]  Ping Chen,et al.  A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.