A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS
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Wei Zhang | Hui Pan | Haitao Tong | Ichiro Fujimori | Seong-Ho Lee | Kambiz Vakilian | Mario Caresosa | Magesh Valliappan | Hamid Hatamkhani | Anthony Brewster | Karo Khanoyan | Duke Tran
[1] P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .
[2] John Wu,et al. A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[3] Simone Erba,et al. A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication , 2009, IEEE Journal of Solid-State Circuits.
[4] John T. Stonick,et al. A digital clock and data recovery architecture for multi-gigabit/s binary links , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[5] Ping Chen,et al. A 250Mb/s-to-3.4Gb/s HDMI receiver with adaptive loop updating frequencies and an adaptive equalizer , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.