High-Performance Pipelined ADCs for Wireless Infrastructure Systems

This chapter provides an overview of design techniques and system aspects relevant to the application of high-speed pipelined ADCs in wireless base transceiver stations (BTS). The discussion begins with a derivation of typical ADC specifications for the receive path of a multi-carrier BTS system. Next, we investigate issues pertaining to the interface between the ADC and its driving circuitry, including complications that arise with sample-and-hold-amplifier-less (SHA-less) ADC frontends. Lastly, we summarize recent research results that look into the digital linearization of dynamic nonlinearities at the ADC’s frontend.

[1]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[2]  Andrew Morgan,et al.  A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration , 2010, IEEE Journal of Solid-State Circuits.

[3]  Manolis Terrovitis,et al.  An 802.11g WLAN SoC , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[4]  Paul R. Gray,et al.  A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter , 1988 .

[5]  S. Devarajan,et al.  A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC , 2009, IEEE Journal of Solid-State Circuits.

[6]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[8]  Phil Brown,et al.  A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC , 2011, 2011 IEEE International Solid-State Circuits Conference.

[9]  Stephen H. Lewis,et al.  A 10-b 20-Msample/s analog-to-digital converter , 1992 .

[10]  J. Kornblum,et al.  A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter , 2006, IEEE Journal of Solid-State Circuits.

[11]  Ling Tian,et al.  A wideband digital pre-distortion platform with 100 MHz instantaneous bandwidth for LTE-advanced applications , 2012, 2012 Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits.

[12]  Matthew Martin,et al.  A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[13]  Boris Murmann,et al.  Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters , 2009, IEEE Journal of Selected Topics in Signal Processing.

[14]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 2000 .