SOC Test Optimization with Compression-Technique Selection

The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.