Investigations on the high current behavior of lateral diffused high-voltage transistors

This paper describes the high current behavior of a lateral, n-channel, high-voltage transistor. The starting points are TCAD experiments where the phenomenological behavior is analyzed. Based on these results a transistor high current model is derived, which is based on the vertical integrated free carrier concentration in the drift region. The important model parameter is the gate voltage, which defines the boundary condition for the free electron concentration at the beginning of the drift region. Because of the coupling of the carrier continuity equation and the Poisson equation (drift-diffusion model), this boundary condition plays a major role, and defines the carrier concentration inside the drift region. Together with an intrinsic low-voltage transistor model (intrinsic NMOS transistor), a series network is solved numerically. The network behavior reflects the TCAD experiments quite well and covers the different electrical regimes (the on-resistance regime, the quasi-saturation regime, and the saturation regime). The model output is compared with the TCAD experiments and the measured transistor data as well.

[1]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[2]  H.R. Claessen,et al.  An accurate DC model for high-voltage lateral DMOS transistors suited for CACD , 1986, IEEE Transactions on Electron Devices.

[3]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[4]  A. W. Ludikhuize,et al.  Kirk effect limitations in high voltage IC's , 1994, Proceedings of the 6th International Symposium on Power Semiconductor Devices and Ics.

[5]  S. Selberherr,et al.  MINIMOS-NT: A Generic Simulator for Complex Semiconductor Devices , 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

[6]  Hussein Ballan,et al.  High Voltage Devices and Circuits in Standard CMOS Technologies , 1998 .

[7]  Adrianus Willem Ludikhuize,et al.  A review of RESURF technology , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[8]  S. Colak,et al.  Effects of drift region parameters on the static properties of power LDMOST , 1981, IEEE Transactions on Electron Devices.

[9]  Philip L. Hower,et al.  Using "Adaptive resurf" to improve the SOA of LDMOS transistors , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[10]  A. Nakagawa,et al.  A new adaptive resurf concept for 20 V LDMOS without breakdown voltage degradation at high current , 1998, Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212).

[11]  C.A.T. Salama,et al.  Optimization of RESURF LDMOS transistors: an analytical approach , 1990 .