A reconfiguration algorithm for delay minimization in VLSI/WSI array processors

Abstract The paper affords the problem of host-driven reconfiguration of VLSI/WSI arrays of processing elements. Aim of the reconfiguration algorithm is to minimize interconnection delays between processing elements. Two different fault models are considered: one refers to random distribution of faults, as may happen in VLSI arrays of relatively large elements; the second one considers cluster of faults and is more tailored to WSI arrays.

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