ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

A design procedure of an all-digital phase-locked loop (ADPLL) based on phase selection mechanism with loop stability independent of process, supply voltage and temperature is presented. A poly-phase filter and a phase interpolator are used to generate multiple phases to reduce the phase error. The modeling of proposed ADPLL structure is extensively investigated and mathematically described. For a phase and a frequency step input change, the closed-loop system of the proposed ADPLL eliminates phase error. Time-domain response of the behavioral-level simulation of the proposed structure on 130-nm CMOS technology with 0.7V supply voltage reveals the presented analytical model.

[1]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[2]  Masayuki Ikebe,et al.  Evaluation of Digitally Controlled PLL by Clock-Period Comparison , 2007, IEICE Trans. Electron..

[3]  Deog-Kyoon Jeong,et al.  An 128-phase PLL using interpolation technique , 2003 .

[4]  Ryuichi Fujimoto,et al.  A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter , 2012, IEICE Trans. Electron..

[5]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  Nicola Da Dalt.  A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Toshimasa Matsuoka,et al.  A low-power CMOS programmable frequency divider with novel retiming scheme , 2015, IEICE Electron. Express.

[8]  L. Maurer,et al.  Be flexible , 2008, IEEE Microwave Magazine.

[9]  Wei Li,et al.  A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO , 2010, IEEE Journal of Solid-State Circuits.

[10]  E. Jury.  A note on the modified stability table for linear discrete time systems , 1991 .

[11]  D.J. Allstot,et al.  An image-rejection down-converter for low-IF receivers , 2005, IEEE Transactions on Microwave Theory and Techniques.

[12]  Asad A. Abidi,et al.  CMOS mixers and polyphase filters for large image rejection , 2001, IEEE J. Solid State Circuits.

[13]  Chen-Yi Lee,et al.  An all-digital phase-locked loop (ADPLL)-based clock recovery circuit , 1999, IEEE J. Solid State Circuits.

[14]  Junho Moon,et al.  Design of a 1.8 V 6-bit Folding Interpolation CMOS A/D Converter with a 0.93 [pJ/convstep] Figure-of-Merit , 2008, IEICE Trans. Electron..

[15]  P. Gregorius,et al.  A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[16]  Ching-Che Chung,et al.  An all-digital phase-locked loop for high-speed clock generation , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[17]  Khurram Muhammad,et al.  Digital RF processing: toward low-cost reconfigurable radios , 2005, IEEE Communications Magazine.

[18]  L. Maurer,et al.  Analysis and Measurement of Spurious Emission and Phase Noise Performance of an RF All-Digital Phase Locked Loop using a Frequency Discriminator , 2007, 2007 IEEE/MTT-S International Microwave Symposium.

[19]  Poras T. Balsara,et al.  Phase-domain all-digital phase-locked loop , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[20]  O. Moreira-Tamayo,et al.  All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.