Placing, Routing, and Editing Virtual FPGAs

This paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA. From a high level description of the FPGA architecture, the basic tools such a placer, a router or an editor are automatically generated. The description is not constrained by any model, so that abstract architectures, such as virtual FPGAs, can directly exploit the tool set as their basic programming tools.

[1]  Vincenzo Piuri,et al.  Virtual FPGAs: Some Steps Behind the Physical Barriers , 1998, IPPS/SPDP Workshops.

[2]  Anant Agarwal,et al.  Virtual wires: overcoming pin limitations in FPGA-based logic emulators , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[3]  Dominique Lavenier,et al.  Systolic filter for fast DNA similarity search , 1995, Proceedings The International Conference on Application Specific Array Processors.

[4]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[5]  Vaughn Betz,et al.  Using Architectural "Families" to Increase FPGA Speed and Density , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[6]  Christopher W. Fraser,et al.  A Retargetable C Compiler: Design and Implementation , 1995 .

[7]  Dominique Lavenier,et al.  Placement of Linear Arrays , 2000, FPL.

[8]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[9]  Bernard Pottier,et al.  Object-oriented meta tools for reconfigurable architectures , 2000, SPIE Optics East.