Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique
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[1] J. T. Horstmann,et al. New fabrication technique for nano-MOS transistors with W=25 nm and L=25 nm using only conventional optical lithography , 2002 .
[2] J. Knoch,et al. Impact of the channel thickness on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors , 2002 .
[3] Schottky source/drain SOI MOSFET with shallow doped extension , 2003 .
[4] J. Snyder,et al. SUB-40 NM PTSI SCHOTTKY SOURCE/DRAIN METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS , 1999 .
[5] J. T. Horstmann,et al. Midbandgap materials for sub-100-nm MOS transistors , 2002 .
[6] C. Yang,et al. Two-dimensional numerical simulation of Schottky barrier MOSFET with channel length to 10 nm , 1998 .
[7] D.S.H. Chan,et al. Schottky-barrier S/D MOSFETs with high-k gate dielectrics and metal-gate electrode , 2004, IEEE Electron Device Letters.
[8] Jae-Heon Shin,et al. A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor , 2004 .
[9] E. Dubois,et al. Schottky-barrier source/drain MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate , 2004, IEEE Electron Device Letters.
[10] S. Winnerl,et al. Fabrication of Schottky barrier MOSFETs on SOI by a self-assembly CoSi2-patterning method , 2003 .
[11] A. Chin,et al. Germanium pMOSFETs with Schottky-barrier germanide S/D, high-/spl kappa/ gate dielectric and metal gate , 2005, IEEE Electron Device Letters.
[12] K. Wang,et al. Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs , 2002, IEEE Electron Device Letters.
[13] Umberto Ravaioli,et al. Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique , 2000 .