Improving Power Efficiency for Active-RC Delta-Sigma Modulators Using a Passive-RC Low-Pass Filter in the Feedback

This brief presents a technique to improve the power efficiency of an active-<italic>RC</italic> 1-bit continuous-time Delta-Sigma modulator (DSM). A passive-<italic>RC</italic> low-pass filter (LPF) is used in feedback after the 1-bit digital-to-analog converter (DAC). The LPF smooths out the rail-to-rail sharp edges of the DAC output to reduce the signal-swing and slew-rate requirements of the first amplifier in DSM. The LPF is also utilized to contribute a pole to the loop response of the modulator. It does not require a compensation filter and reduces the order of the active part of the loop filter. A third-order DSM was designed in a 0.18-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> CMOS process. Measurement results show that it can achieve 79.1-dB SNDR over 100-kHz bandwidth while consuming only 59.1 <inline-formula> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula>.

[1]  Cong Liu,et al.  15.2 A 4.5mW CT self-coupled ΔΣ modulator with 2.2MHz BW and 90.4dB SNDR using residual ELD compensation , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Georges G. E. Gielen,et al.  A 40-MHz Bandwidth 0–2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  B. M. Putter,et al.  /spl Sigma//spl Delta/ ADC with finite impulse response feedback DAC , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4]  Jose Silva-Martinez,et al.  A 43-mW MASH 2-2 CT $\Sigma \Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS , 2017, IEEE Journal of Solid-State Circuits.

[5]  Amrith Sukumaran,et al.  Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback , 2014, IEEE Journal of Solid-State Circuits.

[6]  Shouli Yan,et al.  A 2.7mW 2MHz Continuous-Time ΣΔ Modulator with a Hybrid Active-Passive Loop Filter , 2006, IEEE Custom Integrated Circuits Conference 2006.

[7]  Nuno Paulino,et al.  A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[8]  Patrick Satarzadeh,et al.  A 20mW 61dB SNDR (60MHz BW) 1b 3rd-order continuous-time delta-sigma modulator clocked at 6GHz in 45nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[9]  O. Oliaei,et al.  Sigma-delta modulator with spectrally shaped feedback , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[10]  Pieter Rombouts,et al.  Passive Loop Filter Assistance for CTSDMs , 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Myung-Don Kim,et al.  A Low-Power Continuous-Time Delta-Sigma Modulator Using a Resonant Single Op-Amp Third-Order Loop Filter , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Karthikeyan Reddy,et al.  Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[13]  Kofi A. A. Makinwa,et al.  A continuous-time ΣΔ modulator with a Gm-C input stage, 120-dB CMRR and −87 dB THD , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[14]  Cong Liu,et al.  A 4.5 mW CT Self-Coupled $\Delta\Sigma$ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation , 2015, IEEE Journal of Solid-State Circuits.