Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors

The SpiNNaker project aims to develop parallel computer systems with more than a million embedded processors. The goal of the project is to support large-scale simulations of systems of spiking neurons in biological real time, an application that is highly parallel but also places very high loads on the communication infrastructure due to the very high connectivity of biological neurons. The scale of the machine requires fault-tolerance and power-efficiency to influence the design throughout, and the develop-ment has resulted in innovation at every level of design, including a self-timed inter-chip communic-ation system that is resistant to glitch-induced deadlock and ‘emergency’ hardware packet re-routing around failed inter-chip links, through to run-time support for functional migration and real-time fault mitigation.

[1]  Steve B. Furber,et al.  Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric , 2009, 2009 Eighth International Symposium on Parallel and Distributed Computing.

[2]  Steve B. Furber,et al.  Neural Systems Engineering , 2008, Computational Intelligence: A Compendium.

[3]  Steve Furber,et al.  High-performance computing for systems of spiking neurons , 2006 .

[4]  Steve B. Furber,et al.  Optimal connectivity in hardware-targetted MLP networks , 2009, 2009 International Joint Conference on Neural Networks.

[5]  Stephen B. Furber,et al.  Efficient modelling of spiking neural networks on a scalable chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[6]  Massimo A. Sivilotti,et al.  Wiring considerations in analog VLSI systems, with application to field-programmable networks , 1992 .

[7]  Steve B. Furber,et al.  SpiNNaker: The Design Automation Problem , 2009, ICONIP.

[8]  Steve B. Furber,et al.  The Deferred Event Model for Hardware-Oriented Spiking Neural Networks , 2008, ICONIP.

[9]  Steve B. Furber,et al.  A universal abstract-time platform for real-time neural networks , 2009, 2009 International Joint Conference on Neural Networks.

[10]  Jim D. Garside,et al.  A Programmable Adaptive Router for a GALS Parallel System , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[11]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[12]  Stephen B. Furber,et al.  Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.

[13]  Rufin van Rullen,et al.  Rate Coding Versus Temporal Order Coding: What the Retinal Ganglion Cells Tell the Visual Cortex , 2001, Neural Computation.

[14]  Luis A. Plana,et al.  A GALS Infrastructure for a Massively Parallel Multiprocessor , 2007, IEEE Design & Test of Computers.

[15]  M. M. Khan,et al.  System-level Modelling for SpiNNaker CMP System , 2008 .

[16]  Steve B. Furber,et al.  Evaluating rank-order code performance using a biologically-derived retinal model , 2009, 2009 International Joint Conference on Neural Networks.

[17]  Stephen B. Furber,et al.  Virtual synaptic interconnect using an asynchronous network-on-chip , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[18]  Steve B. Furber,et al.  An admission control system for QoS provision on a best-effort GALS interconnect , 2008, 2008 8th International Conference on Application of Concurrency to System Design.

[19]  Misha Anne Mahowald,et al.  VLSI analogs of neuronal visual processing: a synthesis of form and function , 1992 .

[20]  Luis A. Plana,et al.  SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[21]  Jim D. Garside,et al.  Fault Tolerant Delay Insensitive Inter-chip Communication , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[22]  Andrew D. Brown,et al.  On-chip and inter-chip networks for modeling large-scale neural systems , 2006, 2006 IEEE International Symposium on Circuits and Systems.