This paper describes a framework for realizing low-power digital CMOS circuits using the principles of adiabatic switching. The starting point for all such systems is the observation that in CMOS circuits signal energies need not be dissipated but may be recycled or conserved under the appropriate conditions. From this observation to the point of demonstrating circuits that achieve low-power operation and do so at energy-dissipation levels which are competitive with other approaches to low-power design lie many challenges. This paper delves into the system design problems starting with the design of a simple reversible sequential logic chip that conserves signals energies into and out of the chip and finishes with the design of the necessary power supply elements for sequencing and powering the logic elements.
[1]
William C. Athas,et al.
An energy-efficient CMOS line driver using adiabatic switching
,
1994,
Proceedings of 4th Great Lakes Symposium on VLSI.
[2]
A. Keen.
Amplifying devices and low-pass amplifier design
,
1968
.
[3]
J. Taylor,et al.
Switching and finite automata theory, 2nd ed.
,
1980,
Proceedings of the IEEE.
[4]
Sven Mattisson,et al.
Hot Clock nMOS
,
1985
.
[5]
J. G. Koller,et al.
Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information
,
1992,
Workshop on Physics and Computation.