Reduction methods for adapting optical network on chip topologies to specific routing applications

Abstract — 1 Optical network on chip (ONoC) architectures are emerging as potential contenders to solve congestion and latency issues in future computing architectures. In this work, we examine how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in MPSoCs and heterogeneous SoCs. Through such techniques, it is possible to reduce the number of required wavelengths and routing elements, thereby relaxing constraints on source wavelength accuracy and passive filter selectivity, and also alleviating power and area issues by reducing the number of active devices. Using this method, we show that it is possible to reduce the number of required wavelengths and routing elements by 38% an d 72% respectively, when mapping a full 8 ××××8 ONoC to an 8-node SSTNoC architecture. I. I NTRODUCTION The shift to very high performance distributed Multi-Processor Systems-on-Chip (MPSoC) as mainstream computing devices is the recognized route to address, in particular, power issues by reducing individual processor frequency while retaining the same overall computing power. This rationale answers the need for flexible and scalable computing platforms capable (i) of achieving future required application performance in terms of resolution (audio, video and computing) and CPU power / total MIPS (real-time encoding-decoding, data encryption-decryption), and (ii) of working with multiple standards and with constrained power, which are both particularly important for mobile applications. However, the move to such architectures requires organized high-speed communication between processors and therefore has an impact on the interconnect structure. It clearly relies upon the existence of an extremely fast and flexible interconnect architecture, to such a point that the management of communication between processors will become key to successful development. Aggregated on-chip data transfer rates in MPSoC, such as the IBM Cell processor [1], is critical and is expected to reach over 100Tb/s in the coming decade. As such, interconnects will play a significant role for MPSoC design in order to support these high data rates.