Die stress in stealth dicing for MEMS

Wafer dicing is a necessary and important process in the microelectronics fabrication. Emerging technologies of IC semiconductor have been utilizing silicon-on-insulation (SOI) wafers. These wafers have made wafer dicing quite challenging. Compared to conventional blade dicing, stealth dicing has advantages such as debris-free and dry process. MEMS dies that are fabricated on a SOI wafer and then undergo stealth dicing is studied in this paper. Cracks were found around the edges of the membrane in the MEMS dies after stealth dicing. The failure causes are to be determined. Three processes in the stealth dicing are studied: IR laser scanning, tape dicing and peeling process. Effects of these three processes on the die stresses were investigated. It is the first time that die stresses in a membrane-structured MEMS on SOI wafer in stealth dicing are analyzed. Thermal/structural stress contours are obtained by finite element analysis. Die stresses caused by these three processes are compared.

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