Hierarchical timing analysis using conditional delays

We present a novel method to perform timing analysis of hierarchical circuits. It is based on the representation of circuit modules by conditional delay matrices (CDMs) which combine module delays with event propagation conditions. The CDM model is independent of module complexity and allows automatic identification of false paths. We exploit hierarchy information to perform efficient delay computation. The effectiveness of the method is demonstrated on a high-level model of the ISCAS-85 circuit c6288, which is difficult to analyze using traditional approaches. The method has been implemented in a symbolic timing analysis program called CAT. The application of CAT to carry-skip adders shows that hierarchical timing analysis is faster by an order of magnitude than gate-level analysis.

[1]  Sharad Malik,et al.  Computation of floating mode delay in combinational circuits: theory and algorithms , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Joao Marques-Silva,et al.  Efficient and robust test generation-based timing analysis , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[3]  Kaushik Roy.  The use of RTL descriptions in accurate timing verification and test generation (VLSI) , 1991 .

[4]  Hugo De Man,et al.  Performance Through Hierarchy in Static Timing Verification , 1992, IFIP Congress.

[5]  Enrico Macii,et al.  Timing analysis of combinational circuits using ADDs , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  Jyuo-Min Shyu,et al.  Timed Boolean calculus and its applications in timing analysis , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Robert K. Brayton,et al.  Integrating functional and temporal domains in logic design , 1991 .

[8]  Robert K. Brayton,et al.  Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions , 1993, 30th ACM/IEEE Design Automation Conference.

[9]  Alexander Saldanha.  Performance and testability interactions in logic synthesis , 1992 .

[10]  Sharad Malik,et al.  Certified timing verification and the transition delay of a logic circuit , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[11]  David Hung-Chang Du,et al.  Path sensitization in critical path problem , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[12]  Robert K. Brayton,et al.  Delay Models and Exact Timing Analysis , 1993 .

[13]  John P. Hayes,et al.  High-level test generation using physically-induced faults , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[14]  Régis Leveugle,et al.  Taking advantage of high level functional information to refine timing analysis and timing information , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.