Systematic Design of Pipelined Recursive Filters

Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required. >

[1]  Michael G. Taylor,et al.  Overflow oscillations in digital filters , 1969 .

[2]  John G. McWhirter,et al.  Bit-Level systolic architectures for high performance IIR filtering , 1989, J. VLSI Signal Process..

[3]  Tomás Lang,et al.  On-the-Fly Conversion of Redundant into Conventional Representations , 1987, IEEE Transactions on Computers.

[4]  Keshab K. Parhi,et al.  A fast VLSI adder architecture , 1992 .

[5]  Keshab K. Parhi,et al.  Pipelined VLSI recursive filter architectures using scattered look-ahead and decomposition , 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

[6]  William P. Marnane,et al.  Design and test of a bit parallel 2nd order IIR filter structure , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[7]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[8]  Paul Jespers,et al.  A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor , 1989 .

[9]  Roger Woods,et al.  A 40 megasample IIR filter chip , 1991, Proceedings of the International Conference on Application Specific Array Processors.

[10]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[11]  Keshab K. Parhi,et al.  High-speed VLSI arithmetic processor architectures using hybrid number representation , 1992, J. VLSI Signal Process..

[12]  P. Fortier,et al.  A very fast digital realization of a time-domain block LMS filter , 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

[13]  P. Fortier,et al.  Highly parallel architecture for the least mean squares (LMS) algorithm , 1991, Canadian Journal of Electrical and Computer Engineering.

[14]  S.A. White,et al.  Applications of distributed arithmetic to digital signal processing: a tutorial review , 1989, IEEE ASSP Magazine.

[15]  Milos D. Ercegovac,et al.  On-Line Algorithms for Division and Multiplication , 1977, IEEE Transactions on Computers.

[16]  Paul Fortier,et al.  A new faster and simpler systolic structure for IIR filters , 1990, IEEE International Symposium on Circuits and Systems.