A 1 MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

A 2nd-order continuous-time quadrature bandpass /spl Sigma//spl Delta/ modulator with 1 MHz IF clocked at 100 MHz digitizes I and Q inputs with SNDR of 56.2 dB for 1 MHz bandwidth inputs. The 0.65 /spl mu/m BiCMOS chip consumes 21.8 mW at 2.7 V, and operates with a clock-frequency range of 25-100 MHz.

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