FOWLP: Chip-First and Die Face-Down

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineon on October 31, 2001 (Hedler et al. in Transfer Wafer Level Packaging, 2001 [1]; Lau in Chip Scale Rev. 19:42–46, 2015 [2]), and the first technical papers were also published (at ECTC2006 and EPTC2006) by Infineon and their industry partners: Nagase, Nitto Denko, and Yamada (Brunnbauer et al. in IEEE/ECTC Proceedings, 547–551, 2006 [3]; Brunnbauer et al. in IEEE/EPTC Proceedings, 1–5, 2006 [4]). At that time, they called it embedded wafer-level ball (eWLB) grid array.

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[14]  A. Kumar,et al.  Design and development of a multi-die embedded micro wafer level package , 2008, 2008 58th Electronic Components and Technology Conference.

[15]  John H. Lau,et al.  Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs) , 2017 .

[16]  Jinglin Shi,et al.  High Quality and Low Loss Millimeter Wave Passives Demonstrated to 77-GHz for SiP Technologies Using Embedded Wafer-Level Packaging Platform (EMWLP) , 2010, IEEE Transactions on Advanced Packaging.

[17]  Seung Wook Yoon,et al.  Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[18]  Khong Chee Houe,et al.  Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[19]  J. Bauer,et al.  Large area compression molding for Fan-out Panel Level Packing , 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

[20]  B. Keser,et al.  The Redistributed Chip Package: A Breakthrough for Advanced Packaging , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[21]  H. Hedler,et al.  An embedded device technology based on a molded reconfigured wafer , 2006, 56th Electronic Components and Technology Conference 2006.