Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension

In this paper, we present the unique features exhibited by a proposed structure of coaxially gated carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions using the self-consistent and atomistic scale simulations, within the nonequilibrium Green's function formalism. In this novel CNTFET structure, three adjacent metal cylindrical gates are used, where two side metal gates with lower workfunction than the main gate as an extension of the source/drain on either side of the main metal gate are biased, independent of the main gate, to create virtual extensions to the source and the drain and also to provide an effective electrical screen for the channel region from the drain voltage variations. We demonstrate that the proposed structure of CNTFET shows improvement in device performance focusing on leakage current, on-off current ratio, and voltage gain. In addition, the investigation of short-channel effects for the proposed structure shows improved drain-induced barrier lowering, hot-carrier effect, and subthreshold swing, all of which can affect the reliability of CMOS devices.

[1]  J. Tersoff.  Schottky Barrier Heights and the Continuum of Gap States , 1984 .

[2]  Stefan Kubicek,et al.  Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime , 2000 .

[3]  Ali A. Orouji,et al.  Investigation of the novel attributes of a carbon nanotube FET with high-κ gate dielectrics , 2008 .

[4]  Byung-Gook Park,et al.  A new 50-nm nMOSFET with side-gates for virtual source-drain extensions , 2002 .

[6]  M. Lundstrom,et al.  Ballistic carbon nanotube field-effect transistors , 2003, Nature.

[7]  Mark S. Lundstrom,et al.  Simulation of phonon-assisted band-to-band tunneling in carbon nanotube field-effect transistors , 2005, cond-mat/0510122.

[8]  Ali A. Orouji,et al.  Novel attributes in scaling issues of carbon nanotube field-effect transistors , 2009, Microelectron. J..

[9]  T. Sakamoto,et al.  Transistor operation of 30-nm gate-length EJ-MOSFETs , 1998, IEEE Electron Device Letters.

[10]  Mark S. Lundstrom,et al.  Toward Multiscale Modeling of Carbon Nanotube Transistors , 2004 .

[11]  Mark S. Lundstrom,et al.  High-κ dielectrics for advanced carbon-nanotube transistors and logic gates , 2002 .

[12]  A. Orouji,et al.  Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions , 2005, IEEE Transactions on Electron Devices.

[13]  Eric Polizzi,et al.  Subband decomposition approach for the simulation of quantum electron transport in nanostructures , 2005 .

[14]  R.H. Dennard,et al.  1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints , 1979, IEEE Transactions on Electron Devices.

[15]  F. Hsu,et al.  Structure-enhanced MOSFET degradation due to hot-electron injection , 1984, IEEE Electron Device Letters.

[16]  Reference levels for heterojunctions and Schottky barriers. , 1986, Physical review letters.

[17]  M. J. Kumar,et al.  A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain , 2006 .

[18]  Jong-Ho Lee,et al.  50 nm MOSFET with electrically induced source/drain (S/D) extensions , 2001 .

[19]  A. Orouji,et al.  Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications , 2005, IEEE Transactions on Device and Materials Reliability.

[20]  Richard Martel,et al.  Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes , 2002 .

[21]  Gerhard Klimeck,et al.  Single and multiband modeling of quantum electron transport through layered semiconductor devices , 1997 .

[22]  M. Dresselhaus,et al.  Physical properties of carbon nanotubes , 1998 .

[23]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[24]  S. Datta,et al.  Towards Multi-Scale Modeling of Carbon Nanotube Transistors , 2003, cond-mat/0312551.

[25]  Lex A. Akers,et al.  Ultra large scale integrated microelectronics , 1988 .

[26]  K. Ng,et al.  The Physics of Semiconductor Devices , 2019, Springer Proceedings in Physics.

[27]  S. Datta.  Quantum Transport: Atom to Transistor , 2004 .

[28]  S. Tans,et al.  Room-temperature transistor based on a single carbon nanotube , 1998, Nature.

[29]  Toshitsugu Sakamoto,et al.  Transistor characteristics of 14-nm-gate-length EJ-MOSFETs , 2000 .

[30]  V. Ramgopal Rao,et al.  A novel dynamic threshold operation using electrically induced junction MOSFET in the deep sub-micrometer CMOS regime , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[31]  M. Anantram,et al.  Two-dimensional quantum mechanical modeling of nanotransistors , 2001, cond-mat/0111290.

[32]  S. Datta.  Nanoscale device modeling: the Green’s function method , 2000 .