A new methodology for design of BiCMOS gates and comparison with CMOS
暂无分享,去创建一个
[1] P. Raje,et al. BiCMOS gate performance optimization using a unified delay model , 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.
[2] K. M. Cham,et al. A new BiCMOS/CMOS gate comparison/design methodology and supply voltage scaling model , 1989, International Technical Digest on Electron Devices Meeting.
[3] T. Ikeda,et al. Advanced BiCMOS technology for high speed VLSI , 1986, 1986 International Electron Devices Meeting.
[4] K. Kanzaki,et al. 0.8µm Bi-CMOS technology with high fTion-implanted emitter bipolar transistor , 1987, 1987 International Electron Devices Meeting.
[5] Makoto Suzuki,et al. A 7-ns/350-mW 64-kbit ECL-compatible RAM , 1987 .
[6] I. Masuda,et al. High-speed BiCMOS technology with a buried twin well structure , 1987, IEEE Transactions on Electron Devices.
[7] I. Masuda,et al. Perspective on BiCMOS VLSIs , 1988 .
[8] Yoji Nishio,et al. A BiCMOS logic gate with positive feedback , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.
[9] Masanori Odaka,et al. 13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology , 1986 .