Rapid design space exploration using legacy design data and technology scaling trend

Rapid and effective design space exploration at all stages of a design process enables faster design convergence and shorter time-to-market. This is particularly important during the early stage of a design where design decisions can have a significant impact on design convergence. This paper describes a methodology for design space exploration using design target prediction models. These models are driven by legacy design data, technology scaling trends and, an in situ model-fitting process. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7-32% for a corresponding 0-9% performance impact; or performance centric designs with improved performance of 10.31-17% for a corresponding 2-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.

[1]  Cristian Constantinescu,et al.  Trends and Challenges in VLSI Circuit Reliability , 2003, IEEE Micro.

[2]  M. Celik,et al.  Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  T. Chen,et al.  Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Narayanan Vijaykrishnan,et al.  Impact of technology scaling in the clock system power , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[5]  Rohit Bhatia,et al.  Montecito: a dual-core, dual-thread Itanium processor , 2005, IEEE Micro.

[6]  James Lin Design technology challenges for system and chip level designs in very deep submicron technologies , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[7]  Marco Laumanns,et al.  PISA: A Platform and Programming Language Independent Interface for Search Algorithms , 2003, EMO.

[8]  Ram Krishnamurthy,et al.  A CPL-based dual supply 32-bit ALU for sub 180 nm CMOS technologies , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[9]  John E. Dennis,et al.  Normal-Boundary Intersection: A New Method for Generating the Pareto Surface in Nonlinear Multicriteria Optimization Problems , 1998, SIAM J. Optim..

[10]  M. K. Gowan,et al.  A 65 nm 2-Billion Transistor Quad-Core Itanium Processor , 2009, IEEE Journal of Solid-State Circuits.

[11]  Michael Gschwind,et al.  New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors , 2003, IBM J. Res. Dev..

[12]  Kaushik Roy,et al.  Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Tom Chen,et al.  Design target exploration for meeting time-to-market using pareto analysis , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[14]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[15]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[16]  S. Borkar,et al.  Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[17]  Vincenzo Catania,et al.  A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  S. Rusu,et al.  Trends and challenges in VLSI technology scaling towards 100 nm , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[19]  Kurt Keutzer,et al.  System-Level Performance Modeling with BACPAC - Berkeley Advanced Chip Performance Calculator , 1999 .

[20]  Justin E. Harlow Toward design technology in 2020: trends, issues, and challenges [VLSI design] , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[21]  David Howard,et al.  Challenges in sleep transistor design and implementation in low-power designs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[22]  Poras T. Balsara,et al.  Power switch network design for MTCMOS , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[23]  David Blaauw,et al.  Fast and Accurate Waveform Analysis with Current Source Models , 2008, ISQED 2008.

[24]  Barry Dennington Low Power Design from Technology Challenge to Great Products , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[25]  Kalyanmoy Deb,et al.  Multi-objective optimization using evolutionary algorithms , 2001, Wiley-Interscience series in systems and optimization.

[26]  K. Soumyanath,et al.  Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[27]  Shishpal Rawat,et al.  EDA challenges facing future microprocessor design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[29]  Tom Chen,et al.  Power andPerformance Analysis for Early Design Space Exploration , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[30]  David Blaauw,et al.  Fast and Accurate Waveform Analysis with Current Source Models , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[31]  Tom Chen,et al.  Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models , 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

[32]  Jörg Henkel,et al.  System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[33]  Andy D. Pimentel,et al.  Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design , 2006, IEEE Transactions on Evolutionary Computation.

[34]  Rajendran Panda,et al.  Slope propagation in static timing analysis , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[35]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[36]  S. Hsu,et al.  A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS , 2005, IEEE Journal of Solid-State Circuits.

[37]  Frank Vahid,et al.  Platune: a tuning framework for system-on-a-chip platforms , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Cameron McNairy,et al.  Itanium 2 Processor Microarchitecture , 2003, IEEE Micro.