Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current

This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 °C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only 45 μm × 17 μm.

[1]  K. Nii,et al.  A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications , 2004, IEEE Journal of Solid-State Circuits.

[2]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[3]  M.-R. Lin,et al.  Nickel silicide metal gate FDSOI devices with improved gate oxide leakage , 2002, Digest. International Electron Devices Meeting,.

[4]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[5]  Ming-Dou Ker,et al.  Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit , 2014, Microelectron. Reliab..

[6]  Shih-Hung Chen,et al.  Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  C. Hu,et al.  Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling , 2001 .

[8]  T. Smedes,et al.  ESD protection for high-voltage CMOS technologies , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[9]  D. Singh,et al.  Effect of Temperature Variation on Gate Tunneling Currents in Nanoscale MOSFETs , 2008, 2008 8th IEEE Conference on Nanotechnology.

[10]  L. Register,et al.  Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance , 2003 .

[11]  Ming-Dou Ker,et al.  On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[12]  Ming-Dou Ker,et al.  Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[13]  Ming-Dou Ker,et al.  On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology , 2014, IEEE Transactions on Device and Materials Reliability.

[14]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[15]  Ming-Dou Ker,et al.  SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology , 2005, IEEE Transactions on Semiconductor Manufacturing.

[16]  Ming-Dou Ker,et al.  Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology , 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

[17]  Ming-Dou Ker,et al.  Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits , 2005, IEEE Transactions on Device and Materials Reliability.

[18]  H. Iwai,et al.  1.5 nm direct-tunneling gate oxide Si MOSFET's , 1996 .

[19]  Xing Zhang,et al.  Design and verification of a novel multi-RC-triggered power clamp circuit for on-chip ESD protection , 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

[20]  M. Ker,et al.  Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process , 2013, IEEE Transactions on Electron Devices.