A High Linearity Shunt Capacitive Feedback LNA for Wireless Applications

In this paper, CMOS LNA with low noise and high linearity with shunt capacitive and CS with inductive degenerate topology is presented. LNA is implemented in ADS on 0.18 µm TSMC technology. The LNA is designed for RF Front end so the important parameters are gain, linearity and noise figure. The circuit designed exhibits good I/P and O/P reflection coefficients with low power consumption which is crucial for LNA designing. The circuit attains S11 = −22.06 dB, S12 = −2.77 dB, S21 = 9.4 dB, and S22 = −104.85 dB and NF = 1.23 dB and IIP3 = 56.86 dBm for 6 GHz frequency band, used for future mobile communication or 5G technology.

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