A placement algorithm for implementation of analog LSI/VLSI systems
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[1] J. Litsios,et al. ILAC: an automated layout tool for analog CMOS circuits , 1989 .
[2] Rob A. Rutenbar,et al. Layout tools for analog ICs and mixed-signal SoCs: a survey , 2000, ISPD '00.
[3] Pinaki Mazumder,et al. SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement , 1994, Proceedings of 7th International Conference on VLSI Design.
[4] 田口 玄一,et al. Taguchi methods, research and development , 1992 .
[5] D. F. Wong,et al. Simulated Annealing for VLSI Design , 1988 .
[6] Ulrich Kleine,et al. AN AUTOMATIC LAYOUT DESIGN AID FOR ANALOG INTEGRATED CIRCUITS , 2003 .
[7] Elizabeth M. Rudnick,et al. Genetic algorithms for VLSI design, layout & test automation , 1999 .
[8] J. Litsios,et al. ILAC: an automated layout tool for analog CMOS circuits , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
[9] K. Handa,et al. Polycell placement for analog LSI chip designs by genetic algorithms and tabu search , 1995, Proceedings of 1995 IEEE International Conference on Evolutionary Computation.
[10] Pinaki Mazumder,et al. Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome , 1991, Integr..
[11] Georges Gielen,et al. Analog layout generation for performance and manufacturability , 1999 .
[12] John M. Cohn. Analog Device-Level Layout Automation , 1994 .