Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications

An analytical and continuous model for a highly-doped double-gate Sol MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. (c) 2007 Elsevier Ltd. All rights reserved.

[1]  Adelmo Ortiz-Conde,et al.  Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs , 2005 .

[2]  J. Colinge Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[3]  Y. Taur,et al.  A continuous, analytic drain-current model for DG MOSFETs , 2004 .

[4]  E. Suzuki,et al.  Demonstration, analysis, and device design considerations for independent DG MOSFETs , 2005, IEEE Transactions on Electron Devices.

[5]  H. A. Hamid,et al.  Explicit continuous model for long-channel undoped surrounding gate MOSFETs , 2005, IEEE Transactions on Electron Devices.

[6]  D. Flandre,et al.  Modeling of ultrathin double-gate nMOS/SOI transistors , 1994 .

[7]  Yiming Li,et al.  A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs , 2005, IEEE Transactions on Nanotechnology.

[8]  Christian Enz,et al.  A Design Oriented Charge-based Current Model for Symmetric DG MOSFET and its Correlation with the EKV Formalism , 2005 .

[9]  J. Sáenz,et al.  Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field-effect-transistor , 2003 .

[10]  Denis Flandre,et al.  FinFET analogue characterization from DC to 110 GHz , 2005 .

[11]  J.-P. Raskin,et al.  Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization , 2006, IEEE Transactions on Electron Devices.

[12]  J. Sáenz,et al.  Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits , 2004 .

[13]  Denis Flandre,et al.  Moderate Inversion Model of Ultrathin Double-gate Nmos/soi Transistors , 1995 .

[14]  Denis Flandre,et al.  A physically-based C/sub /spl infin//-continuous fully-depleted SOI MOSFET model for analog applications , 1996 .

[15]  G. Pei,et al.  A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description , 2003 .

[16]  Daniel Mathiot,et al.  A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs , 2002 .