Parallel Computer Systems Testing and Integration

The ever-growing complexity of computer systems testing is becoming more important than ever. With today’s technology we are capable of building the systems that may contain in a cage or a frame several millions of circuits which, even with high level integration, may have to be packaged in several hundred thousand chips. The quest for testing in multiprocessors is a very challenging one and it is our intent to shed some light on this important, but frequently underestimated, aspect of implementing large parallel computers.

[1]  T. Sridhar.  A New Parallel Test Approach for Large Memories , 1986, IEEE Design & Test of Computers.

[2]  Jacob A. Abraham,et al.  Efficient Algorithms for Testing Semiconductor Random-Access Memories , 1978, IEEE Transactions on Computers.

[3]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[4]  Jacob A. Abraham,et al.  Test Generation for Microprocessors , 1980, IEEE Transactions on Computers.

[5]  M. Ray Mercer,et al.  Testability Measures : What Do They Tell Us ? , 1982, ITC.

[6]  Jordi Duran,et al.  Application of signature analysis to the concurrent test of microprogrammed control units , 1987 .

[7]  Miroslaw Malek,et al.  A Fault-Tolerant FFT Processor , 1988, IEEE Trans. Computers.

[8]  Arthur D. Friedman,et al.  System-Level Fault Diagnosis , 1980, Computer.

[9]  GERNOT METZE,et al.  On the Connection Assignment Problem of Diagnosable Systems , 1967, IEEE Trans. Electron. Comput..

[10]  Prathima Agrawal,et al.  RAFT: A Recursive Algorithm for Fault Tolerance , 1985, ICPP.

[11]  Kewal K. Saluja,et al.  A Novel Approach for Testing Memories Using a Built-In Self Testing Technique , 1986, International Test Conference.

[12]  Tse-Yun Feng,et al.  Fault-Diagnosis for a Class of Multistage Interconnection Networks , 1981, IEEE Trans. Computers.

[13]  John P. Hayes,et al.  Testability Considerotions in Microprocessor-Based Design , 1980, Computer.

[14]  Fabrizio Grandoni,et al.  A Theory of Diagnosability of Digital Systems , 1976, IEEE Transactions on Computers.

[15]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[16]  Miroslaw Malek,et al.  Cost-effective error detection codes in multicomputer networks , 1987 .

[17]  Jacob A. Abraham,et al.  Algorithm-Based Fault Tolerance for Matrix Operations , 1984, IEEE Transactions on Computers.

[18]  John F. Wakerly,et al.  Error detecting codes, self-checking circuits and applications , 1978 .

[19]  Gerald M. Masson,et al.  Diagnosable Systems for Intermittent Faults , 1978, IEEE Transactions on Computers.

[20]  Miroslaw Malek,et al.  Real-Time Diagnosis of Banyan Networks , 1982, RTSS.

[21]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[22]  S. L. Hakimi,et al.  System-level fault diagnosis: A survey , 1987 .

[23]  S. Louis Hakimi,et al.  Characterization of Connection Assignment of Diagnosable Systems , 1974, IEEE Transactions on Computers.

[24]  L. H. Goldstein,et al.  Controllability/observability analysis of digital circuits , 1978 .

[25]  G. Jack Lipovski,et al.  Parallel computing - theory and comparisons , 1987 .

[26]  Miroslaw Malek,et al.  A comparison connection assignment for diagnosis of multiprocessor systems , 1980, ISCA '80.