Reliability challenges in Forksheet Devices: (Invited Paper)

The forksheet (FSH) device architecture is a possible candidate towards continued logic cell downscaling. It consists of vertically stacked n- and p-type sheets at opposing sides of a dielectric wall. In this work, we overview the time-0 and time-dependent performance of n and p-type FSH field-effect transistors co-integrated with nanosheets (NSH) in individual wafers. A separate assessment of dedicated capacitors yields indications of a non-negligible effect of negative fixed charges trapped in low-temperature deposited SiO2, currently used as dielectric wall liner. Finally, we evaluate the impact of using a bottom dielectric isolation (BDI) instead of a junction-based electrical isolation of the sheets from the substrate.

[1]  H. Mertens,et al.  Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures , 2022, 2022 International Electron Devices Meeting (IEDM).

[2]  H. Mertens,et al.  Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets , 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

[3]  H. Mertens,et al.  Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs , 2022, 2022 IEEE International Reliability Physics Symposium (IRPS).

[4]  F. M. Bufler,et al.  Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond , 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

[5]  H. Mertens,et al.  Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space , 2021, 2021 Symposium on VLSI Technology.

[6]  J. Kavalieros,et al.  Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application , 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

[7]  C. Park,et al.  Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[8]  A. De Keersgieter,et al.  Understanding and Physical Modeling Superior Hot-Carrier Reliability of Ge pNWFETs , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[9]  J. Ryckaert,et al.  Novel forksheet device architecture as ultimate logic scaling device towards 2nm , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[10]  L. Larcher,et al.  A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From ${I}$ – ${V}$ , ${C}$ – ${V}$ , and ${G}$ – ${V}$ Measurements , 2019 .

[11]  H. Mertens,et al.  Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors with Reduced Vertical Nanowires Separation, New Work Function Metal Gate Solutions, and DC/AC Performance Optimization , 2018, International Electron Devices Meeting.

[12]  S. Jung,et al.  3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications , 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

[13]  Dimitri Linten,et al.  Self-heating-aware CMOS reliability characterization using degradation maps , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[14]  Anisur Rahman,et al.  Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[15]  J. Ryckaert,et al.  Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[16]  X. Garros,et al.  Hot carrier degradation in nanowire transistors: Physical mechanisms, width dependence and impact of Self-Heating , 2016, 2016 IEEE Symposium on VLSI Technology.

[17]  S. Chew,et al.  Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[18]  T. Grasser,et al.  Ubiquitous relaxation in BTI stressing—New evaluation and insights , 2008, 2008 IEEE International Reliability Physics Symposium.

[19]  Karl Hess,et al.  A Multi-Carrier Model for Interface Trap Generation , 2002 .

[20]  L. Larcher,et al.  A Sensitivity Map-Based Approach to Profile Defects in MIM Capacitors From ${I}$ – ${V}$ , ${C}$ , 2019, IEEE Transactions on Electron Devices.

[21]  Tibor Grasser,et al.  Understanding and Modeling the Temperature Behavior of Hot-Carrier Degradation in SiON nMOSFETs , 2016, IEEE Electron Device Letters.