Semiconductor memory device capable of test time reduction within pipeline

PURPOSE: A semiconductor memory device for reducing data test time is provided to test the memory device using only one clock signal transmitted through a comparison control portion connected to a last end of a pipeline structure, thereby reducing the data test time. CONSTITUTION: A unit pipeline cell(10) is connected with each of data lines to latch data in data line. The first pipeline set is connected to a plurality of unit pipeline cells in series, which are connected to a group of data lines, to transmit the data to a next unit pipeline cell and then output the data in the group of data lines. The second pipeline set is connected to the plurality of unit pipeline cells in series, which are connected to the rest group of data lines, to transmit the data to a next unit pipeline cell and then output the data in the rest group of data lines. The first comparing portion is connected to a last terminal of the unit pipeline cell when performing a test operation to test the data in the data line, which is provided to a DQ block.