Area-efficient high-speed 3D DWT processor architecture
暂无分享,去创建一个
[1] Panos Nasiopoulos,et al. Lossless Compression of 4D Medical Images using H.264/AVC , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.
[2] Yong Liu,et al. Design and implementation of an RNS-based 2-D DWT processor , 2004, IEEE Transactions on Consumer Electronics.
[3] Danny Crookes. Architectures for high performance image processing: The future , 1999, J. Syst. Archit..
[4] Swapna Banerjee,et al. A memory efficient 3-D DWT architecture , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[5] Indrajit Chakrabarti,et al. An efficient hardware implementation of DWT and IDWT , 2003, TENCON 2003. Conference on Convergent Technologies for Asia-Pacific Region.
[6] Wael Badawy,et al. A low power prototype for a 3D discrete wavelet transform processor , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[7] Joan Carletta,et al. A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.
[8] Fred J. Taylor,et al. Fast implementation of orthogonal wavelet filterbanks using field-programmable logic , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).
[9] Edward J. Delp,et al. Wavelet based rate scalable video compression , 1999, IEEE Trans. Circuits Syst. Video Technol..