Reducing power dissipation during at-speed test application

Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%.

[1]  Y. Zorian,et al.  Power-/Energy Efficient BIST Schemes for Processor Data Paths , 2000, IEEE Des. Test Comput..

[2]  Serge Pravossoudovitch,et al.  Reducing power consumption during test application by test vector ordering , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[3]  Zhongcheng Li,et al.  Reduction of Number of Paths to be Tested in Delay Testing , 2000, J. Electron. Test..

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Yervant Zorian,et al.  A distributed BIST control scheme for complex VLSI devices , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[6]  Huawei Li,et al.  An approach to reducing power consumption during delay test application , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).

[7]  S. Chakravarty,et al.  Two techniques for minimizing power dissipation in scan circuits during test application , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).