A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories
暂无分享,去创建一个
[1] Kinam Kim,et al. Technology challenges for deep-nano semiconductor , 2010, 2010 IEEE International Memory Workshop.
[2] Takamaro Kikkawa,et al. Scaling challenge of Self-Aligned STI cell (SA-STI cell) for NAND flash memories , 2013 .
[3] Jae-Duk Lee,et al. A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.
[4] K. Takeuchi,et al. Error-prediction analyses in 1X, 2X and 3Xnm NAND flash memories for system-level reliability improvement of solid-state drives (SSDs) , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).
[5] Sungjoo Hong,et al. Novel Negative $Vt$ Shift Phenomenon of Program–Inhibit Cell in $\hbox{2}X{-}\hbox{3}X\hbox{-}\hbox{nm}$ Self-Aligned STI nand Flash Memory , 2012, IEEE Transactions on Electron Devices.
[6] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[7] Shuhei Tanakamaru,et al. Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.
[8] Chilhee Chung,et al. New scaling limitation of the floating gate cell in NAND Flash Memory , 2010, 2010 IEEE International Reliability Physics Symposium.
[9] Ki-Tae Park. A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing Program Scheme for Sub-40nm MLC NAND Flash Memories and beyond , 2007, 2007 IEEE Symposium on VLSI Circuits.
[10] J. Kessenich,et al. Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.
[11] Tanaka,et al. A Multi-page Cell Architecture For High-speed Programming Multi-level NAND Flash Memories , 1997, Symposium 1997 on VLSI Circuits.