On reconfigurable fabrics and generic side-channel countermeasures

The use of field programmable devices in security-critical applications is growing in popularity; in part, this can be attributed to their potential for balancing metrics such as efficiency and algorithm agility. However, in common with non-programmable alternatives, physical attack techniques such as fault and power analysis are a threat. We investigate a family of next-generation field programmable devices, specifically those based on the concept of time multiplexing, within this context: our results support the premise that extra, inherent flexibility in such devices can offer a range of possibilities for low-overhead, generic countermeasures against physical attack.

[1]  Paul C. Kocher,et al.  Differential Power Analysis , 1999, CRYPTO.

[2]  Mark G. Karpovsky,et al.  Power attacks on secure hardware based on early propagation of data , 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

[3]  Ingrid Verbauwhede,et al.  Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration , 2008, CHES.

[4]  Sri Parameswaran,et al.  MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[5]  Kai Liu,et al.  Research on Time Randomization of AES against Differential Power Analysis , 2009, 2009 Second International Symposium on Computational Intelligence and Design.

[6]  Mark Zwolinski,et al.  Divided Backend Duplication Methodology for Balanced Dual Rail Routing , 2008, CHES.

[7]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[8]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[9]  Michael Tunstall,et al.  Efficient Use of Random Delays in Embedded Software , 2007, WISTP.

[10]  Thomas Popp,et al.  Evaluation of Power Estimation Methods Based on Logic Simulations , 2007 .

[11]  Tim Güneysu,et al.  Generic Side-Channel Countermeasures for Reconfigurable Devices , 2011, CHES.

[12]  Sri Parameswaran,et al.  Differential Power Analysis in AES: A Crypto Anatomy , 2011 .

[13]  Henk L. Muller,et al.  Non-deterministic Processors , 2001, ACISP.

[14]  Ingrid Verbauwhede,et al.  A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Ingrid Verbauwhede,et al.  Place and Route for Secure Standard Cell Design , 2004, CARDIS.

[16]  Kamal Chaudhary,et al.  Performance-oriented fully routable dynamic architecture for a field programmable logic dervice , 1993 .

[17]  Steven Trimberger,et al.  A time-multiplexed FPGA , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).

[18]  Daisuke Suzuki,et al.  Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style , 2006, CHES.

[19]  Bart Preneel,et al.  Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? , 2004, CHES.

[20]  Jean-Sébastien Coron,et al.  An Efficient Method for Random Delay Generation in Embedded Software , 2009, CHES.

[21]  Sylvain Guilley,et al.  The "Backend Duplication" Method , 2005, CHES.

[22]  Stefan Mangard,et al.  Successfully Attacking Masked AES Hardware Implementations , 2005, CHES.

[23]  Jean-Sébastien Coron,et al.  Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems , 1999, CHES.

[24]  Thomas Zefferer,et al.  Evaluation of the Masked Logic Style MDPL on a Prototype Chip , 2007, CHES.