论文信息 - A bit-serial VLSI architecture for the 2-D discrete cosine transform

A bit-serial VLSI architecture for the 2-D discrete cosine transform

Abstract In this paper, a VLSI architecture for the computation of the 2-D N × N -point Discrete Cosine Transform (DCT) is presented, where N is a power of 2. The proposed bit-serial architecture has highly regular structure and exhibits high data throughput rate. It is based on a high performance application specific multiplier. A chip was designed for the computation of the 4 × 4-point DCT exhibiting a performance of 246 M pixels/sec.

Anna Tatsaki | Costas Goutis

[1] Masahiko Yoshimoto,et al. A 100-MHz 2-D discrete cosine transform core processor , 1992 .

[2] R. Gnanasekaran,et al. On a Bit-Serial Input and Bit-Serial Output Multiplier , 1983, IEEE Transactions on Computers.

[3] M. Liou,et al. A concurrent architecture for VLSI implementation of discrete cosine transform , 1987, IEEE Transactions on Circuits and Systems.

[4] Yianni Attikiouzel,et al. An efficient algorithm for computing two-dimensional discrete cosine transforms , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[5] N. Ahmed,et al. Discrete Cosine Transform , 1996 .

[6] Ting Chen,et al. VLSI implementation of a 16*16 discrete cosine transform , 1989 .