Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming
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[1] M. D. F. Wong,et al. Floorplan design for multi-million gate FPGAs , 2004, ICCAD 2004.
[2] Seda Ogrenci Memik,et al. Placement and Floorplanning in Dynamically Reconfigurable FPGAs , 2010, TRETS.
[3] Elaheh Bozorgzadeh,et al. Multi-layer Floorplanning on a Sequence of Reconfigurable Designs , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[4] Igor L. Markov,et al. Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[5] Susmita Sur-Kolay,et al. Floorplanning for Partially Reconfigurable FPGAs , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Yao-Wen Chang,et al. Temporal floorplanning using the three-dimensional transitive closure subGraph , 2007, TODE.
[7] Marco D. Santambrogio,et al. Wirelength driven floorplacement for FPGA-based partial reconfigurable systems , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).
[8] Chiara Sandionigi,et al. Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.
[9] Yan Feng,et al. Heterogeneous floorplanning for FPGAs , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[10] Kizheppatt Vipin,et al. Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration , 2012, ARC.
[11] Yoji Kajitani,et al. VLSI module placement based on rectangle-packing by the sequence-pair , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..