论文信息 - A 45 nm 8-Core Enterprise Xeon¯ Processor

A 45 nm 8-Core Enterprise Xeon¯ Processor

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

[1] N. Kurd,et al. Next generation Intel® micro-architecture (Nehalem) clocking architecture , 2008, 2008 IEEE Symposium on VLSI Circuits.

[2] Yong-Gee Ng,et al. A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology , 2009, IEEE Journal of Solid-State Circuits.

[3] Uddalak Bhattacharya,et al. A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4] R. Chau,et al. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[5] R. Varada,et al. Design and Integration Methods for a Multi-threaded Dual Core 65nm Xeon® Processor , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.