Design of On-Chip ESD Protection Circuits with Consideration of Gate-Oxide Reliability

The aim of this thesis is to propose solutions of ESD protection problems under the consideration of gate-oxide reliability. Objectives of the proposed designs are to achieve the desired ESD protection capabilities in circuit technique without modifying process steps or increasing mask layers. Therefore, the proposed designs are suitable to different CMOS processes and therefore can be widely applied to different circuit designs. The first proposal is a gate-voltage-limited circuit that can clamp the coupled gate voltage of an gate-coupled NMOS device during ESD transition. The over-coupled gate voltage of an NMOS device draws over-huge ESD current in the channel region and burns out the gate oxide of the NMOS device. The gate-voltage-limited circuit can therefore prevent the gate-coupled devices from the over-gate-driven effect. This design was fabricated and verified in a 0.35-μm CMOS process. Experimental results show that a gate-coupled NMOS with the proposed gate-voltage-limited circuit can have a 30% improvement on its MM ESD protection level compared to a gate-coupled NMOS without the proposed circuit. The second proposal is a power-rail ESD clamp circuit. The specialty of this proposed design is that it is designed with only 1-V and 2.5-V low voltage devices to be operated under the 3.3-V high power-supply voltage without the gate oxide reliability issue. This proposed design can collocate with mixed-voltage I/O designs to achieve a higher circuit operation frequency. This iii proposed design was fabricated and verified in a 0.13-μm 1-V/2.5-V CMOS process. Experimental results show that the proposed design has extremely small standby leakage current under the normal circuit operating condition. This design also shows fast turn-on speed under ESD stresses and high ESD protection robustness.

[1]  C. Duvvury,et al.  Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.

[2]  Steven H. Voldman,et al.  Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[3]  Timothy J. Maloney,et al.  Novel clamp circuits for IC power supply protection , 1995 .

[4]  Chung-Yu Wu,et al.  Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[5]  G. Notermans.  On the use of n-well resistors for uniform triggering of ESD protection elements , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[6]  D. B. Krakauer,et al.  ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration , 1998 .

[7]  C. Duvvury,et al.  Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes , 1998 .

[8]  G. P. Singh,et al.  High-voltage-tolerant I/O buffers with low-voltage CMOS process , 1999, IEEE J. Solid State Circuits.

[9]  M. Ker.  Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI , 1999 .

[10]  Tung-Yang Chen,et al.  Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-/spl mu/m silicided process , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[11]  Tung-Yang Chen,et al.  ESD buses for whole-chip ESD protection , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[12]  Timothy J. Maloney,et al.  Stacked PMOS clamps for high voltage power supply protection , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[13]  S. Voldman.  The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling , 1999 .

[14]  C.C. Russ,et al.  Wafer cost reduction through design of high performance fully silicided ESD devices , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[15]  Ming-Dou Ker,et al.  Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS process , 2000, IEEE Journal of Solid-State Circuits.

[16]  Tung-Yang Chen,et al.  Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices , 2001 .

[17]  Kevin Barraclough,et al.  I and i , 2001, BMJ : British Medical Journal.

[18]  Kaustav Banerjee,et al.  Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors , 2002 .

[19]  Timothy J. Maloney,et al.  New considerations for MOSFET power clamps , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[20]  Ming-Dou Ker,et al.  Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers , 2002 .

[21]  Kaustav Banerjee,et al.  Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs , 2002 .

[22]  Ming-Dou Ker,et al.  ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique , 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

[23]  Ming-Dou Ker,et al.  Latchup-free ESD protection design with complementary substrate-triggered SCR devices , 2003 .

[24]  Tung-Yang Chen,et al.  Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process , 2003 .

[25]  Ming-Dou Ker,et al.  ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness , 2003 .

[26]  Ming-Dou Ker,et al.  Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[27]  Harald Gossner.  ESD protection for the deep sub micron regime - a challenge for design methodology , 2004, 17th International Conference on VLSI Design. Proceedings..

[28]  K.-H. Lin,et al.  On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process , 2004, IEEE Transactions on Electron Devices.

[29]  吉谷 正章,et al.  Electrostatic discharge protection circuit and a semiconductor device , 2006 .

[30]  Ming-Dou Ker,et al.  Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.