Power transition X filling based selective Huffman encoding technique for test-data compression and Scan Power Reduction for SOCs

Abstract Due to the excessive utilization of memory, data compression is an evergreen research topic. Realizing the constant demand of compression algorithms, this article presents a compression algorithm to analyse the digital VLSI circuits for constraint optimization, such as test data volume, switching power, chip area overhead and processing speed of testing. This article proposes a new power transition X filling based selective Huffman encoding technique, which achieves better data compression, switching power reduction, chip area overhead reduction and speed of testing. The performance of the proposed work is examined with the help of ISCAS benchmark circuits. Initially, the test set is occupied by using the power transition X filling technique to replace the don't care bits and the filled test set is further encoded by selective Huffman encoding technique. The experimental results show that the proposed power transition X filling based selective Huffman encoding gives effective results compared to the related data compression techniques with minimal time and memory consumption.