An Artificial Neural Net Viterbi Decoder

Artificial neural networks (ANN’S) have been successfully applied in the fields of signal processing and pattern recognition In recent years, efforts have been made to design ANN decoders for error control codes. Although the general decoding problem can be viewed as a form of pattern recognition (PR), the information capacity in an error control code is far more extensive than tha t contained in most PR problems. Because of this, neural net training, a popular design tool for ANN, has not fared well in ANN decoders. So far, trained ANN decoders are limited to very small codes like the (7,4) Hamming code and convolutional codes with no more than 2 memory elements. Meanwhile, algebraic structures of the error control codes are not efficiently used in trained ANN decoders, resulting in inferior performance relative to that of the conventional decoders. For these reasons, the design of ANN decoders has become a process of “neuralizing” the existing digital decoding algorithms which have themselves been derived by fully exploiting the algebraic properties of the codes. The decoding process can be maximally parallelized by neural riets, which greatly increases the decoder throughput. Such ANN decoders have been successfully designed for many important block codes, such as Hamming codes, the (24,12) Golay code and the (32,16) QR code [l]. This paper presents an ANN Viterbi decoder for convolutional codes. In the past, Viterbi decoders have always been implemented using digital circuits. The speed of these digital decoders is directly related to the amount of parallelism in the design. As the constraint length of the code increases, parallelism becomes problematic due to the complexity of the decoder. In this work i t is shown that the register exchange type [2] of VA can be completely represented by an ANN structure. However, for large decoding depth r , the required dynamic range goes far beyond what an analog neuron can provide. Sinte the register exchange operation is digital in essence, it is natural t o adopt a hybrid design, which is shown in Figure 1 for a standard rate-1/2 code with 2 memory elements. The analog part of the design implements the input correlation and path selection, as well as a scaling algorithm to keep each neuron holding the partial metric from saturating. The inputs to the decoder are T O and T I from the binary signalling AWGN channel. All connection gains are +1 unless mal ked otherwise. The synchronization circuit is not shown in the figure to preserve clarity, The structure in Figure 1 can be Easily extended to rate-k/n convolutional codes with M memory elements. The complexity of a locally connected neural network is characterized by the number of neurons, N. In general N is found to be N = 2’(2k+2 2) + 2n + 1