A Parallel Current-steering DAC Architecture for Flexible and Improved Performance

This paper presents a new current-steering DAC architecture for flexible and improved performance. This flexible DAC architecture is based on fixed entities: sub-DACs. They are nominally identical and operate in parallel, which results in improved and flexible performance, delivered in several modes of operation (OP). One OP mode is using the sub-DACs as independent converters. Another option is using them together for higher conversion resolution and accuracy. This paper concentrates on a particular OP mode, which through distributing the input digital word among the parallel sub-DACs, achieves cancellation of the mismatch errors. This technique leads to improved static linearity, whereas the improvement depends on the occupied pre-processing resources. The proposed technique can be fully integrated on-chip, as it relies on a 1bit ADC and makes reuse of already existing resources.