Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures

Abstract A Full Adder (FA) is the basic building block of many VLSI sub-systems, and generally it falls into the critical path of the system. Several Transmission Gate (TG) and hybrid CMOS FA designs have been proposed in literature to achieve low Power Delay Product (PDP). But, their performance degrades when used in chain and tree structures, mainly due to poor driving capability. This paper introduces new design approach, a triplet design, to improve performance of TG and hybrid CMOS FA designs in chain and tree structures without inserting buffers. Two new hybrid CMOS FA designs, which are suitable for triplet design approach are also proposed in this paper. Six different FA designs (TG and hybrid CMOS FAs) are chosen to build 4, 8 and 16 bit Ripple Carry Adders (RCA) and multipliers, and we also studied the improvement in PDP using triplet design approach. Schematics and layouts of RCA and multiplier are designed in Cadence Virtuoso using gpdk045 library, and compared based on PDP.

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