Layout-aware pseudo-functional testing for critical paths considering power supply noise effects

When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of the circuits. In this paper, we propose novel layout-aware pseudo-functional testing techniques to tackle the above problem. Firstly, by taking the circuit layout information into account, functional constraints related to delay faults on critical paths are extracted. Then, we generate functionally-reachable test cubes for every true critical path in the circuit. Finally, we fill the don't-care bits in the test cubes to maximize power supply noises on critical paths under the consideration of functional constraints. The effectiveness of the proposed methodology is verified with large ISCAS'89 benchmark circuits.

[1]  Mark Mohammad Tehranipoor,et al.  Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths , 2009, 2009 27th IEEE VLSI Test Symposium.

[2]  Kwang-Ting Cheng,et al.  Path selection and pattern generation for dynamic timing analysis considering power supply noise effects , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  Xiaoqing Wen,et al.  Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[4]  Qiang Xu,et al.  On systematic illegal state identification for pseudo-functional testing , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[5]  Qiang Xu,et al.  SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects , 2008, 2008 IEEE International Test Conference.

[6]  Guido Gronthoud,et al.  Modeling Power Supply Noise in Delay Testing , 2007, IEEE Design & Test of Computers.

[7]  Peter C. Maxwell,et al.  Comparing functional and structural tests , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  P. Krishnamurthy.  Power-Aware DFT - Do we really need it? , 2008 .

[9]  Shlomi Sde-Paz,et al.  Frequency and Power Correlation between At-Speed Scan and Functional Tests , 2008, 2008 IEEE International Test Conference.

[10]  Irith Pomeranz,et al.  On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[11]  Michael S. Hsiao,et al.  A Study of Implication Based Pseudo Functional Testing , 2006, 2006 IEEE International Test Conference.

[12]  Kwang-Ting Cheng,et al.  Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Kaushik Roy,et al.  Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[14]  Susmita Sur-Kolay,et al.  A modeling approach for addressing power supply switching noise related failures of integrated circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[15]  Kwang-Ting Cheng,et al.  Pseudofunctional testing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Qiang Xu,et al.  Compression-aware pseudo-functional testing , 2009, 2009 International Test Conference.

[17]  Irith Pomeranz,et al.  Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs , 2006, 2006 IEEE International Test Conference.

[18]  Yu Hu,et al.  iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing , 2008, 2008 Design, Automation and Test in Europe.

[19]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Irith Pomeranz,et al.  Scan-Based Tests with Low Switching Activity , 2007, IEEE Design & Test of Computers.

[21]  Michael S. Hsiao,et al.  A novel transition fault ATPG that reduces yield loss , 2005, IEEE Design & Test of Computers.

[22]  Qiang Xu,et al.  Pattern-directed circuit virtual partitioning for test power reduction , 2007, 2007 IEEE International Test Conference.