A 10ps 500MHz time-to-digital converter in 0.18μm CMOS technology for ADC

This paper presents a 10ps 500MHz time-to-digital converter (TDC) in 0.18μm CMOS technology. Based on the Vernier delay line structure, the TDC can achieve high resolution, high speed and a dynamic range of 0 ~ 640ps. To increase the accuracy, the delay line cells are designed using full-custom design method. Additional, the delay cells are divided into 6 groups along the long horizontal direction of layout to have a good tradeoff between the accuracy and complexity. Another two blocks pipelined readout circuit and encoder are designed in semi-custom method to reduce the design complexity. A built-in test block generating different time interval is also embedded in the TDC to facilitate the measurement. This TDC has been tapped out and the total area including I/O pads is 1252μm×705μm. Post simulation results indicate that the TDC can work correctly at 500MHz and have a resolution of 10ps.

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