Synthesis of multiple outputs CMOS gates

Design of static CMOS gates for multiple output functions is presented. Two techniques for minimization of multiple output functions at the switching level are introduced. These techniques are based on innovative transistor interconnection structures named delta and lambda networks. Design examples on double output functions are provided. It is shown that the two techniques can be combined together, if necessary, to obtain further area reductions.<<ETX>>

[1]  F. Hohn A matrix method for the design of relay circuits , 1955, IRE Transactions on Circuit Theory.

[2]  Nripendra N. Biswas,et al.  BANGALORE: an algorithm for the optimal minimization of programmable logic arrays , 1986 .

[3]  William W. Cohen,et al.  A Rule-Based System for Optimizing Combinational Logic , 1985, IEEE Design & Test of Computers.

[4]  Raymond E. Miller,et al.  Formal Analysis and Synthesis of Bilateral Switching Networks , 1958, IRE Trans. Electron. Comput..

[5]  Louise Trevillyan,et al.  Logic Synthesis Through Local Transformations , 1981, IBM J. Res. Dev..

[6]  Michel Dagenais,et al.  McBOOLE: A New Procedure for Exact Logic Minimization , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Robert K. Brayton,et al.  An exact minimizer for Boolean relations , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[8]  K. Goto Five methods for simplification of logic function and comparison of their characteristics , 1990, IEEE International Symposium on Circuits and Systems.

[9]  Daniel L. Ostapko,et al.  MINI: A Heuristic Approach for Logic Minimization , 1974, IBM J. Res. Dev..