Low power and pipelined secure hashing algorithm-3(SHA-3)

Cryptography plays an important role in the security of data. Even though the data is encrypted it can be altered while transmitting on the network so data should be verified using a digital signature. Hashing algorithms are used to create these digital signatures for verification of the data received. Hashing algorithm like Secure hash algorithm-3 SHA-3(512) (keccak) is designed which has a fixed output length of 512-bits. Then to improve on power a low-power technique such as latch based clock gating technique is used. After applying these techniques all the designs are compared in terms of power, delay and frequency. SHA-3 algorithm is designed using Verilog HDL and simulated in Xilinx ISE v14.2.

[1]  Morris J. Dworkin,et al.  SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions , 2015 .

[2]  George Athanasiou,et al.  High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm , 2014, 2014 6th International Symposium on Communications, Control and Signal Processing (ISCCSP).

[3]  Liwei Zhang,et al.  Towards secure cryptographic software implementation against side-channel power analysis attacks , 2015, 2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP).

[4]  Liang Han,et al.  Hardware implementation analysis of SHA-3 candidates algorithms , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[5]  Ashish Kumar,et al.  Analyzing the performance and security by using SHA3 in WEP , 2015, 2015 IEEE International Conference on Engineering and Technology (ICETECH).

[6]  Sahu,et al.  Review on Clock Gating Techniques , 2015 .

[7]  Artemios G. Voyiatzis,et al.  High performance pipelined FPGA implementation of the SHA-3 hash algorithm , 2015, 2015 4th Mediterranean Conference on Embedded Computing (MECO).

[8]  Arshad Aziz,et al.  Compact implementation of SHA3-512 on FPGA , 2014, 2014 Conference on Information Assurance and Cyber Security (CIACS).

[9]  P. Krishna Sankar,et al.  Redundant file finder, remover in mobile environment through SHA-3 algorithm , 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

[10]  Samir Palnitkar,et al.  Verilog HDL: a guide to digital design and synthesis , 1996 .