The development of ultra-high-frequency VLSI device test systems

The development of test systems for high-performance semiconductor logic and memory devices is discussed. The capabilities of shared-resource and tester-per-pin system architectures are reviewed. Test-system hardware design to provide high-speed pin electronics and generation of LSSD, weighed random, and algorithmic patterns is described. The reasons for the selection of the tester-per-pin system architecture are given in terms of the way in which overall system accuracy and test-system user flexibility are maximized for differing test methodologies.