A Fine Resolution TDC Architecture for Next Generation PET Imaging

A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS, is designed to operate over a reference clock frequency of 500 MHz but can be scaled to multi GHz operation through time interleaving. Without external calibration, the TDC is used as a 5-bit fine resolution converter with 4.65 ENOB (effective number of bits). Under this condition, the 6-bit TDC has an INL (integral non-linearity) measurement of less than 1.45 LSB and a DNL (differential non-linearity) measurement of less than 1.25 LSB. With external calibration, a reduction of more than 50% in INL/DNL nonlinearities is demonstrated improving the ENOB to 5.5 bits, pushing the TDC to a 6-bit fine resolution operation. The TDC has a 31 ps timing resolution and power consumption of less than 1 mW. The design is believed to be the fastest and the lowest power consuming fine resolution TDC in the literature.

[1]  Willy Sansen,et al.  A CMOS time to digital converter IC with 2 level analog CAM , 1994 .

[2]  Hen-Wai Tsao,et al.  A high-precision time-to-digital converter using a two-level conversion scheme , 2003, 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515).

[3]  Stefanos Sidiropoulos,et al.  High performance inter-chip signalling , 1998 .

[4]  M. E. Casey,et al.  Coincidence detection and selection in positron emission tomography using VLSI , 1989 .

[5]  J. Benlloch,et al.  High-speed data acquisition and digital signal Processing system for PET imaging techniques applied to mammography , 2004, IEEE Transactions on Nuclear Science.

[6]  Keisuke Asai,et al.  Development of Ultra-Fast Semiconducting Scintillators Using Quantum Confinement Effect , 2004 .

[7]  Donald G. Mitchell,et al.  A CMOS time-of-flight system-on-a-chip for spacecraft instruments , 2002 .

[8]  Nasser A. Kurd,et al.  A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor , 2001, IEEE J. Solid State Circuits.

[9]  Y. Arai,et al.  A time digitizer CMOS gate-array with a 250 ps time resolution , 1996, IEEE J. Solid State Circuits.

[10]  D. B. Crosetto.  System design and verification process for LHC programmable trigger electronics , 1999, 1999 IEEE Nuclear Science Symposium. Conference Record. 1999 Nuclear Science Symposium and Medical Imaging Conference (Cat. No.99CH37019).

[11]  W. Moses,et al.  Prospects for time-of-flight PET using LSO scintillator , 1999 .

[12]  W. Moses,et al.  :Ce Scintillators for Gamma-Ray Spectroscopy , 2003 .

[13]  J. Kostamovaara,et al.  An integrated time-to-digital converter with 30-ps single-shot precision , 2000, IEEE Journal of Solid-State Circuits.

[14]  Poras T. Balsara,et al.  1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  J. M. Rochelle,et al.  A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications , 2004, IEEE Journal of Solid-State Circuits.

[16]  W. Moses,et al.  LaBr/sub 3/:Ce scintillators for gamma ray spectroscopy , 2002, 2002 IEEE Nuclear Science Symposium Conference Record.

[17]  R. Fontaine,et al.  Real time coincidence detection system for digital high resolution APD-based animal PET scanner , 2005, IEEE Nuclear Science Symposium Conference Record, 2005.

[18]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.