General method for phase-locked loop filter analysis and design
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[1] Floyd M. Gardner,et al. Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.
[2] F. Gardner,et al. Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..
[3] Keith Bryan Hardin,et al. Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility , 1997, IEEE 1997, EMC, Austin Style. IEEE 1997 International Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.97CH36113).
[4] S. Goldman. Jerk Response of a Third-Order Phase-Lock Loop , 1976, IEEE Transactions on Aerospace and Electronic Systems.
[5] Alfonso Carlosena,et al. Phase-locked loop design for on-chip tuning applications , 2000 .
[6] H. Blinchikoff,et al. All-Pole Phase-Locked Tracking Filters , 1982, IEEE Trans. Commun..
[7] R. C. Tausworthe,et al. Improvements in deep-space tracking by use of third-order loops. , 1972 .
[8] Paul H. Lewis,et al. A Comparison of Second, Third, and Fourth Order Phase-Locked Loops , 1967, IEEE Transactions on Aerospace and Electronic Systems.
[9] Shahriar Mirabbasi,et al. Design of loop filter in phase-locked loops , 1999 .
[10] Pavan Kumar Hanumolu,et al. Analysis of charge-pump phase-locked loops , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] William F. Egan,et al. Phase-Lock Basics , 1998 .
[12] Dan H. Wolaver,et al. Phase-Locked Loop Circuit Design , 1991 .
[13] W.G. Garrett,et al. A 50 MHz phase- and frequency-locked loop , 1979, IEEE Journal of Solid-State Circuits.
[14] S. C. Gupta,et al. Transient Analysis of a Phase-Locked Loop Optimized for a Frequency Ramp Input , 1964, IEEE Transactions on Space Electronics and Telemetry.
[15] Sebastian Magierowski,et al. Phase Locked Loop gain shaping for gigahertz operation , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[16] M. Steyaert,et al. A fully integrated CMOS DCS-1800 frequency synthesizer , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[17] Alfonso Carlosena,et al. Design of High-Order Phase-Lock Loops , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.
[18] Paul V. Brennan,et al. Fourth-order PLL loop filter design technique with invariant natural frequency and phase margin , 2005 .
[19] Zuoding Wang. An analysis of charge-pump phase-locked loops , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.
[20] V. F. Kroupa,et al. Phase-lock loops of higher orders , 1989 .
[21] Salvatore Levantino,et al. Fast-switching analog PLL with finite-impulse response , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).